Digital storage oscilloscopes are a type of oscilloscope in which an input analog signal is sampled rapidly at periodic intervals and converted to a series of digital values representing the amplitude of the input signal as it varies over time. U.S. Pat. No. 4,779,028 to Blair for "Digital Storage Oscilloscope with Marker for Trigger Location", hereby incorporated by reference, describes the basic operation of digital storage oscilloscopes.
As in analog oscilloscopes, a "trigger" signal determines when a data acquisition is to begin. The trigger signal is used to activate a timebase generator which then produces a very stable and reproducible set of strobe signals. Simple triggers are generated whenever a selected signal crosses a particular voltage threshold. More complex forms of trigger generation have been developed. See for example, U.S. Pat. No. 4,585,975 to Wimmer for "High Speed Boolean Logic Trigger Oscilloscope Vertical Amplifier with Edge Sensitivity and Nested Trigger" or U.S. Pat. No. 5,097,147 to Stuebing for "Limited Amplitude Signal Trigger Circuit", both hereby incorporated by reference. U.S. Pat. No. 4,812,769 to Agoston for "Programmable Sampling Time Base Circuit", hereby incorporated by reference, describes a timebase circuit for a waveform sampling system that produces a strobe signal after an adjustable strobe delay interval.
An oscilloscope front end designed for the rapid acquisition of digital samples representative of the behavior analog signals is described in U.S. Pat. No. 5,144,525 to Saxe et al. for "Analog Acquisition System Including a High Speed Timing Generator", hereby incorporated by reference. Another high speed, fast-in slow-out (FISO) acquisition system is described in U.S. Pat. No. 4,271,488 to Saxe for a "High-Speed Acquisition System Employing an Analog Memory Matrix", hereby incorporated by reference.
The captured analog samples must be converted to multi-bit digital representations of the actual instantaneous voltage value that was present at the time that the sample was taken. U.S. Pat. Nos. 4,774,498 to Traa for "Analog-to-Digital Converter with Error Checking and Correction Circuits", 4,908,621 to Polonio et al for "Autocalibrated Multistage A/D Converter", and 4,985,702 to Penney for "Analog to Digital Converter with Second Order Error Correction", each hereby incorporated by reference, all describe prior art techniques pertaining to analog-to-digital conversion.
The digital values obtained by sampling the analog input signal and performing analog-to-digital conversion are normally stored in an acquisition memory at sequential addresses. Each address location then contains a digital value representing the amplitude of the input signal at a time that is proportional to its relative address number. In the case of repetitive waveforms, the same result can be achieved even if all of the data is not acquired at once. U.S. Pat. No. 4,495,586 to Andrews for "Waveform Acquisition Apparatus and Method", hereby incorporated by reference, describes how waveform data may be built up over time by partially sampling the waveform on successive occurrences. This method has come to be known as "equivalent time" sampling and is further discussed in U.S. Pat. No. 4,809,189 to Batson for "Equivalent Time Waveform Data Display", hereby incorporated by reference.
The digital values representing the behavior of the analog signal can then be presented on an oscilloscope display in several ways. In each of these approaches, the times between samples are converted to distance along the horizontal axis of the display according to the timebase selected by the operator, e.g., one millisecond per division. The sampling rate itself may also be increased or decreased according to the selected timebase so that the record length of the storage memory more closely corresponds to a full screen of displayed data. The stored digital value for each horizontal location is then converted to a vertical distance on the screen and a dot is display at the resulting coordinate. The absolute relationship between the digital values and vertical screen location also depends on operator selected settings of vertical gain and offset controls.
When the number of sample points is sparse, a line can be drawn between successive dots to give the impression of a continuous analog signal, such as would have been displayed by an analog oscilloscope. U.S. Pat. No. 4,251,814 to Dagostino for "Time Dot Display for a Digital Oscilloscope", hereby incorporated by reference, describes a display in which acquired data is shown intensified relative to interpolated data. Interpolated data can also be used to perform automatic waveform measurements, such as pulse width measurements, when the underlying data is sparse.
When a large number of sample points are available, various decimation techniques can be employed to simplify the data and make it more meaningful. One such technique is to identify the minimum and maximum amplitude values within a particular time interval (longer than the sampling interval), and then display a vertical bar extending from the minimum to the maximum amplitudes over the portion of the display corresponding to the particular time interval. U.S. Pat. No. 4,039,784 to Quarton et al. for "Digital Minimum/Maximum Vector CRT Display", and U.S. Pat. No. 4,713,771 to Crop for "Digital Minimum-Maximum Value Sequence Processor", both hereby incorporated by reference, provide background on min/max displays.
Logic analyzers are digital data acquisition instruments that allow a user to acquire and analyze digital data from a large number of logic signals, such as all of the address, data, and control signals associated with a microprocessor. The behavior of groups of these signals can then be monitored to analyze the behavior of the system under test. Each logic signal is compared to a logic threshold and resolved into one of two logic states, or when dual thresholds are used into one of three states, the two basic logic states and an intermediate "unstable" state. The two logic states are variously referred to as high or low, one or zero, true or false, while signals that are determined to be between logic states by dual threshold analysis are said to be "unstable" or "in transition". U.S. Pat. No. 4,968,902 to Jackson for "Unstable Data Recognition Circuit for Dual Threshold Synchronous Data", hereby incorporated by reference, describes circuitry for detecting when one or more signals under analysis are between logic thresholds. U.S. Pat. No. 5,043,927, also to Jackson, for "Digital Signal Quality Analysis Using Simultaneous Dual-Threshold Data Acquisition", also hereby incorporated by reference, describes a method for finding a variety of signal anomalies in a repetitive signal using movable dual thresholds in a succession of measurements on a repetitive waveform.
In logic analyzer data acquisition using a single threshold, the input signal is applied to a voltage comparator whose other input is the voltage threshold that defines the boundary between the two logic states. The output of this comparator is a binary signal that rapidly transitions between high and low levels whenever the analog input signal crosses the logic threshold. Upon the occurrence of active edges of an acquisition clock signal, one or the other of these logic levels is stored in a flip-flop or similar circuit for further processing.
The time at which the state of the logic signals under analysis is resolved into binary form is determined by a clock signal. If this clock signal is generated by the logic analyzer and is independent of the system under test, the acquisition is said to be "asynchronous". If the clock signal is derived from the system under test so as to bear a predetermined timing relationship to at least part of the activity within that system, the acquisition is said to be "synchronous".
Data that is originally synchronous to the user's system clock must be resynchronized to the internal clock of the logic analyzer for further processing. U.S. Pat. No. 4,949,361 to Jackson for "Digital Data Transfer Synchronization Circuit and Method", hereby incorporated by reference, describes circuitry for accomplishing this task efficiently.
Typically, asynchronous data acquisition is relatively rapid and is used for analyzing the "timing" of circuit hardware. And, synchronous data acquisition is typically relatively slower and is used for analyzing the "state" of the system during software execution. U.S. Pat. No. 4,425,643 to Chapman et al. for a "Multi-Speed Logic Analyzer", hereby incorporated by reference, describes a logic analyzer with two sections capable of operating in conjunction with two different clocks. This type of architecture permits coordinated state and timing analysis. U.S. Pat. No. 4,763,117 to Blattner et al. for "Measurement Instruments with Multiple Operation Levels", hereby incorporated by reference, shows a logic analyzer having different modes for basic operation, advanced timing analysis, advanced state analysis, and full operation.
Once data is acquired from two different clock signals (also referred to as "timebases") that are asynchronous to each other and therefore "unrelated", methods must be found to make their relative timing relationships available to the operator of the logic analyzer. U.S. Pat. No. 4,558,422 to DenBeste et al. for a "Digital Signal Sampling System with Two Unrelated Sampling Timebases", and U.S. Pat. No. 4,578,666 to Anderson for a "Method of Comparing Data with Asynchronous Timebases", both hereby incorporated by reference, both describe ways of handling data so that an accurate display of timing relationships is presented to the operator.
Another approach to keeping track of the sampling time associated with different events is the use of "timestamps". Timestamps are a count that is stored when each sample is acquired, and which can then later be used for a variety of purposes. U.S. Pat. No. 4,731,768 to Easterday for "Autoranging Time Stamp Circuit", hereby incorporated by reference, describes one approach to timestamp generation.
The data in the system under analysis may suffer from a variety of defects that distinguish it from theoretically ideal digital data, i.e., data that goes from one stable and well defined logic state to another in an appropriate transition. Data may contain "glitches" or be unstable in some other way, or the data transition may suffer from slow rise or fall times, or exhibit other less-than-ideal behaviors. U.S. Pat. No. 4,353,032 to Taylor for "Glitch Detector", hereby incorporated by reference, describes glitches and a circuit for capturing information about them.
Since logic analyzers acquire signals across a large number of channels simultaneously, and the signal paths through the input circuitry of the logic analyzer or the probes used to connect to the user's system may not be all exactly equivalent electrically, the propagation times of signals passing through these different paths may not be all the same. When this occurs, one signal is said to exhibit "skew" in relation to a another signal. U.S. Pat. No. 4,646,297 to Palmquist et al. for "Skew Detector", hereby incorporated by reference, describes a circuit for detecting this condition. U.S. Pat. No. 4,481,647 to Gombert et al. for "Method and Apparatus of Compensating for Variations in Signal Propagation Time Existing Within the Channels of a Multi-Channel Device", hereby incorporated by reference, describes means for correcting skew errors.
The "resolution" of a logic analyzer is typically .+-.1/2 of the acquisition clock period, e.g., 10 ns for a 100 MHz clock. U.S. Pat. No. 4,979,177 to Jackson for "Enhanced Counter/Timer Resolution in a Logic Analyzer", hereby incorporated by reference, describes a logic analyzer with the ability to use two phases of the system clock to acquire data and then maintain the resulting improved resolution as the data is manipulated internally using a single phase clock. The result is an effectively doubled resolution, e.g., 5 ns for a 100 MHz clock. Another approach is described in U.S. Pat. No. 4,777,616 to Moore et al. for "Increased Resolution Logic Analyzer Using Asynchronous Sampling", hereby incorporated by reference. This approach relies on repeatedly sampling a repetitive signal asynchronously to increase the effective resolution.
All synchronous digital circuitry requires a certain degree of stability of its inputs in order to guarantee appropriate and reliable behavior of its outputs. The time that inputs must be stable before a synchronizing event in order to assure proper operation is known as "setup time", while the time that inputs must be stable after the synchronizing event to assure proper operation is known as "hold time". A logic analyzer also has setup and hold times of its own. Normally, the setup time of a logic analyzer is as short as possible and its hold time is zero.
A conventional logic analyzer typically does some processing of a user's clock signal before using it to acquire synchronous data. Since this processing takes some time, the data signals that are to be clocked also must be delayed in order to position the setup and hold time window appropriately. The inclusion of delay lines on every channel adds a significant amount to the price of a logic analyzer. Moreover, equalizing the resulting delays can add additional expense and complexity. If every delay line is adjustable, channel-to-channel skew can be minimized and the setup and hold window can be moved. Even though putting adjustable delay lines on every channel is quite expensive, it has frequently been done in order to make logic analyzers with suitable specifications. Since the setup and hold time for the whole logic analyzer is only as good as its worst channel, channel-to-channel skew degrades the instrument's overall setup and hold time performance as well as having a variety of other detrimental effects.
Several efforts have been made to combine some of the features of logic analyzers with those of oscilloscopes. The Hewlett-Packard 16500 series and the Tektronix Prism 3000 logic analyzers each offer plug-in modules with digital storage oscilloscope capabilities and displays that allow time correlated viewing of the digital and analog signals acquired at the same time. These instruments permits their users to alternatively look at signals with a logic analyzer perspective or a digital storage oscilloscope perspective. The latter perspective is helpful for looking at the details of a logic signal, its shape, rise and fall times, ringing, undershoot and overshoot, etc. The model 1600 Logic Oscilloscope made by Outlook Technology allows the user to switch between a 200 MHz logic analyzer mode and a 350 MHz, 100 Msample/sec digital storage oscilloscope mode. Biomation Corporation offers an instrument identified as the K1600 Analog Logic Analyzer which is a digital storage oscilloscope with logic timing-analyzer triggering.
None of the oscilloscope and logic analyzer module combinations use the same set of acquired analog data samples for both oscilloscope type displays and logic analyzer type displays. In each of these instruments, when the user selects a logic display, data for that display is acquired in traditional logic analyzer fashion, i.e., storing samples from the output of a comparator which has already resolved the signal into a digital logic level before it is sampled.